1. Field of the Invention
The present invention relates to a semiconductor device having an SOI (Silicon-on-Insulator) substrate.
2. Description of the Related Art
The utmost objective in the field of semiconductor devices is to increase the integration density of the devices. It is demanded that the integration density of a dynamic RAM (hereinafter referred to as "DRAM") be increased to impart to the DRAM a storage capacity of 4 megabits, 16 megabits and more bits.
The higher the integration density of a DRAM, the smaller the capacitance of the memory cells. Inadequate capacitance of the memory cells results in an increase in soft error. Each memory cell of most large-capacity DRAMs recently developed has a capacitor of so-called stack structure. This is because a capacitor of this structure has a large diffusion layer and therefore causes almost no soft error.
FIGS. 97 to 100 show a conventional DRAM which incorporates capacitors of stacked structure. More correctly, FIGS. 97 and 98 illustrate the memory cell section of the DRAM, and FIGS. 99 and 100 the peripheral circuit section of the DRAM.
The memory cell section will be first described. As shown in FIGS. 97 and 98, a field oxide film 13 is provided on the surface of the p-type silicon substrate 11. The film 13 has openings, through which some surface regions of the substrate 11 are exposed. These surface regions are element regions (i.e., source-drain-gate regions). Those surface regions of the substrate 11 which are located right below the filed oxide film 13 are p.sup.- -type impurity regions 32 which serve as channel stoppers.
Two memory cells are provided in each element region and share one drain region. Each memory cell is comprised of one MOS transistor and one capacitor. The MOS transistor has a gate electrode 15, source and drain regions 19, and low impurity concentration regions 16. A gate insulating film 14 is interposed between the silicon substrate 11 and the gate electrode 15. The capacitor has a storage node 21, a capacitor insulating film 22 and a plate electrode 23. The storage node 21 contacts the source region of the MOS transistor. The plate electrode 23 covers all silicon substrate 11, but limited portion of the drain region of the MOS transistor. A bit line 26 is connected to the drain region of the MOS transistor. As shown in FIG. 97, the bit line 26 extends straight, at right angles to a word line (i.e., the gate electrode 15 of the MOS transistor).
The peripheral circuit section will now be described. As shown in FIGS. 99 and 100, a field oxide film 13 is provided on the p-type silicon substrate 11. The film 13 has openings, through which some surface regions of the substrate 11 are exposed. These surface regions are element regions (i.e., source-drain-gate regions). Those surface regions of the substrate 11 which are located right below the field oxide film 13 are p.sup.- -type impurity regions 32 and n-type impurity regions 33, which serve as channel stoppers.
In some of the element regions of the peripheral circuit section, there are provided n-channel MOS transistors. In the remaining element regions of the peripheral circuit region, there are provided p-channel MOS transistors.
Each n-channel MOS transistor has a gate electrode 15, source and drain regions 19, and low impurity concentration regions 16. A gate insulating film 14 is interposed between the silicon substrate 11 and the gate electrode 15.
Similarly, each p-channel MOS transistor has a gate electrode 15, source and drain regions 20, and low impurity concentration regions 17. A gate insulating film 14 is interposed between the silicon substrate 11 and the gate electrode 15.
How the RAM shown in FIGS. 97 to 100 is manufactured will be explained.
First, the field oxide film 13 is formed on the silicon substrate 11. A resist pattern is then formed on the field oxide film 13. Using the resist pattern as a mask, boron is ion-implanted into the silicon substrate 11, forming a p-type impurity region 39 in the surface of the substrate 11. Further, using the resist pattern as a mask, phosphorus is ion-implanted into the silicon substrate 11, forming an n-type impurity region 40 in the surface of the substrate 11.
Next, a gate insulating film 14, a phosphorus-containing polysilicon film, and a TEOS film are formed one upon another, on the resultant structure. A resist pattern is formed on the TEOS film. Using this resist pattern as mask, the TEOS film and the polysilicon film are etched, thereby forming gate electrodes 15.
A resist pattern is then formed on the resultant structure. Using this resist pattern and the gate electrodes 15 as masks, phosphorus is ion-implanted into the n-channel MOS transistor regions of the structure. At the same time, using the resist pattern as a mask, boron is ion-implanted into the p-channel MOS transistor regions of the structure.
Then, the structure is annealed, thereby forming n-type impurity regions 16 and p-type impurity regions 17, all having low impurity concentration. A spacer 18 is formed on the sides of each gate electrode 15. Using the resist pattern again as a mask, arsenic is ion-implanted into the n-channel MOS transistor regions. Using the resist pattern as mask, boron is ion-implanted into the p-channel MOS transistor regions. Further, the structure is subjected to thermal oxidation, thus forming source and drain of n.sup.+ -type and source and drain regions 20, of p.sup.+ -type.
The storage nodes 21 of capacitors are formed on the source regions of the n-channel MOS transistors of the memory cell section. Capacitor insulating films 22 (e.g., a two-layered film consisting of an oxide film and a nitride film) are formed on the storage nodes 21. A phosphorus-containing polysilicon film is formed on the upper surface of the resultant structure.
Thereafter, those parts of the polysilicon film which are located on the drain regions of the n-type MOS transistors provided in the memory cell section are removed, thereby forming the plate electrodes 23 of the capacitors. A BPSG film 24 is then formed on the upper surface of the resultant structure. Contact holes 25 are made in those parts of the BPSG film which contact the drain regions of the n-channel MOS transistors of the memory cell section. On the BPSG film 24, bit lines 26 are formed, connected to the drain regions of the n-channel MOS transistors of the memory cell section.
An inter-layer insulating film 27 is formed on the upper surface of the structure. Contact holes 28 are made in those parts of the BPSG film 24 and inter-layer insulating film 27 which are located on the source and drain regions 19, and source and drain regions 20 of the MOS transistors provided in the peripheral circuit section. Metal wires 29 are formed on the inter-layer insulating film 27. The wires 29 are connected to the source and drain regions 19, and source and drain regions 20 of the MOS transistors.
Thereafter, an inter-layer insulating film, other metal wires and a passivation film are formed, and pads are then formed. The DRAM is thereby manufactured.
The conventional DRAM is disadvantageous in the following respects:
(1) The capacitance of the junction between the source regions and drain region of each MOS transistor increases in proportion to the integration density, making it difficult to read data from the DRAM at high speed.
(2) The higher the integration density, the greater is the possibility that soft error is made in the memory cell section. The residual radioactive element (U, Th or the like) in any semiconductor film undergoes alpha decay, emitting .alpha. rays as shown in FIGS. 101 and 102. The a rays enter the silicon substrate 11, generating hole-electron pairs therein. The electrons of these pairs may move into the capacitor-of a memory cell storing data "1" (i.e., no electrons accumulated in the capacitor). When the electrons in the capacitor increase to a number greater than a specific value, the data "1", stored in the memory cell inevitably changes to data "0" (a sufficient number of electrons accumulated in the capacitor).
(3) It is difficult to apply, as is often desired, a back-gate bias to the switching MOS transistor of each memory cell and to the MOS transistors constituting some of the peripheral circuits (e.g., sense amplifiers). Unless a back-gate bias is applied to any MOS transistor used in, for example, a sense amplifier, the threshold voltage of the transistor will become unstable due to substrate-floating effect. This effect reduces the data-reading tolerance of the DRAM.
(4) A metal silicide layer is provided between the source-drain region of any MOS transistor and a metal wire (electrode) in a peripheral circuit, in order to decrease the contact resistance so that the peripheral circuit may operate fast. This layer is likely to pass through the source-drain region, increasing the leakage current remarkably and ultimately increasing the power consumption.
Accordingly, a first object of the present invention is to provide a DRAM memory cell section which has high integration density, which consumes but a little power, and which scarcely makes soft error.
A second object of the invention is to provide means for applying, whenever necessary, a back-gate bias to the MOS transistors used in the memory cells of a DRAM or the MOS transistors incorporated in some of the peripheral circuits of the DRAM.
A third object of this invention is to provide means for applying a back-gate bias to MOS transistors which require the back-gate bias and applying no backgate bias to MOS transistors which do not require the back-gate bias, thereby to reduce the junction capacitance of these MOS transistors.
A fourth object of the present invention is to provide a metal silicide layer between the source-drain region and a metal wire (electrode), such that the layer would not pass through the source-drain region.
A fifth object of the invention is to provide means for reducing the junction capacitance of MOS transistors which requires no back-gate bias and for improving the performance of an input protecting circuit.